(a) Fields of the Invention
The present invention relates to semiconductor devices, and in particular to electrostatic protection semiconductor devices capable of protecting their internal elements against breakdown due to an electrostatic surge or the like.
(b) Description of Related Art
Recently, with increasing packing density and decreasing power consumption of a semiconductor integrated circuit device, a driver for driving an inductive load has also been requested to increase the packing density and decrease the power consumption.
Herein, the inductive load is a load to which a voltage is applied from outside to pass a current and to generate an induced voltage having a polarity opposite to that of the applied voltage. A concrete example of the inductive load is a motor.
However, a semiconductor device having a driver for driving the inductive load formed therein requires avoiding misoperation of a driver element for driving the inductive load and of an element directly connected to that element.
One exemplary technique for attaining this object is disclosed in Japanese Unexamined Patent Publication No. S61-189662 (referred hereinafter to as Document 1). This technique disclosed is that an island region is provided between a driver element and other circuit elements and the potential of the island region is kept high to prevent misoperation of these elements. Another exemplary technique is disclosed in Japanese Unexamined Patent Publication No. H10-256484 (referred hereinafter to as Document 2). This technique disclosed is that a surge protection element is placed sufficiently away from a driver element.
The technique for avoiding misoperation mentioned in Document 1 will be described below with reference to the accompanying drawings.
FIG. 8 is an equivalent circuit diagram of a semiconductor device mentioned in Document 1.
The semiconductor device includes an output pad 11 electrically connected to an inductive load (not shown), and a driver element 12 electrically connected to the output pad 11 and supplying a current. At a connecting point N11 positioned between the output pad 11 and the driver element 12, a negative surge absorbing unit 13 and a positive surge absorbing unit 14 are electrically connected to each other.
In this device, the negative surge absorbing unit 13 is provided with a negative surge protection diode 15 and a GND (grounding) terminal 16. The negative surge protection diode 15 has a cathode 15K electrically connected to the connecting point N11 and an anode 15A connected to the GND terminal 16. With such a configuration, if the output pad 11 has a negative potential to generate a surge, the negative surge protection diode 15 is activated to absorb the negative surge.
The positive surge absorbing unit 14 is provided with a positive surge protection diode 17 and a power supply terminal 18. The positive surge protection diode 17 has a cathode 17K connected to the power supply terminal 18 and an anode 17A electrically connected to the connecting point N11. With such a configuration, if the output pad 11 has a positive potential to generate a surge, the positive surge protection diode 17 is activated to absorb the positive surge.
Next, FIGS. 9 and 10 are views showing the structure of the negative surge absorbing unit 13 and its peripheral portion in the semiconductor device. FIG. 9 is a sectional view and FIG. 10 is a plan view. In these figures, other components of the semiconductor device shown in FIG. 8, such as the output pad 11 and the driver element 12, are provided at locations in the device which are not shown in FIGS. 9 and 10.
In the semiconductor device 20 shown in FIG. 9, an n-type epitaxial layer 22 is formed on a p-type semiconductor substrate 21, and LOCOS (local oxidation of silicon) films 23 are formed at predetermined positions on the surface of the n-type epitaxial layer 22. The n-type epitaxial layer 22 is divided into multiple regions by a p-type isolation layer 24. To be more specific, the p-type isolation layer 24 defines a protection diode region 25, an n-type peripheral region 26, a control circuit region 27, and other regions.
In this structure, the p-type isolation layer 24 is composed of a heavily p-doped layer 24a formed in and below the surface of the n-type epitaxial layer 22, a p-type upper isolation layer 24b formed below the heavily p-doped layer 24a, and a p-type lower isolation layer 24c formed below the p-type upper isolation layer 24b to extend across the p-type semiconductor substrate 21 and the n-type epitaxial layer 22.
In each of the protection diode region 25, the n-type peripheral region 26 and the control circuit region 27, an n-type buried layer 28 is formed at and through the interface between the p-type semiconductor substrate 21 and the n-type epitaxial layer 22.
In each of the protection diode region 25 and the n-type peripheral region 26, the surface of the n-type epitaxial layer 22 is formed with a heavily n-doped layer 29, while in the control circuit region 27, the surface of the n-type epitaxial layer 22 is formed with a p-type resistive layer 30.
An interlayer insulating film 31 is formed to cover the n-type epitaxial layer 22 and the components formed on its surface. The interlayer insulating film 31 is formed with openings, which are formed with contacts 32 for providing electrical connections to the heavily p-doped layer 24a and the heavily n-doped layer 29 of the protection diode region 25, the heavily n-doped layer 29 of the n-type peripheral region 26, and the p-type resistive layer 30.
Note that the connecting point N11, a terminal with a fixed potential V, a terminal with a GND potential, and the like are also shown in FIG. 9. However, these components are shown simply for the purpose of illustrating electrical connections from corresponding portions of the semiconductor device to these components, and these components are not shown as part of the structure of the device.
Also, as shown in FIG. 10, the p-type isolation layer 24 defines the protection diode region 25, the n-type peripheral region 26, and the control circuit region 27 to surround them. Note that the LOCOS film 23 and the interlayer insulating film 31 are omitted in FIG. 10.
In the control circuit region 27, in addition to a resistance element using the p-type resistive layer 30, required electric elements such as a transistor 33 are formed.
In the protection diode region 25 of this device, the contacts 32 provided on the p-type isolation layer 24 are grounded to the GND potential terminal, and the heavily n-doped layer 29 is electrically connected to the connecting point N11. In the n-type peripheral region 26 thereof, the heavily n-doped layer 29 is electrically connected to the fixed potential terminal having a higher potential than the GND potential.
Since the device has the structure described above, the negative surge protection diode 15 is formed in the protection diode region 25 (see also FIG. 8). To be more specific, the negative surge protection diode 15 is formed which uses the p-type isolation layer 24 and the p-type semiconductor substrate 21 as the anode 15A, and the n-type buried layer 28, the n-type epitaxial layer 22, and the heavily n-doped layer 29 as the cathode 15K.
If the output pad 11 electrically connected to the inductive load has a negative potential, a parasitic NPN transistor 51 is activated which is composed of the n-type peripheral region 26, the p-type isolation layer 24 included in the p-type semiconductor substrate 21 and the protection diode region 25, and the heavily n-doped layer 29 of the protection diode region 25. As a consequence of this, a current is supplied mainly from the n-type peripheral region 26 serving as a collector of the parasitic NPN transistor 51, so that only a reduced amount of current flows through the p-type semiconductor substrate 21.
Also in this device, a parasitic thyristor 52 is formed to extend from the p-type resistive layer 30 of the control circuit region 27 to the heavily n-doped layer 29 of the protection diode region 25. This may cause misoperation of the control circuit region 27. However, the parasitic thyristor 52 has a configuration less likely to be activated.
Specifically, part of the p-type semiconductor substrate 21 included in the n-type peripheral region 26 serves as a p-type gate portion. The presence of the n-type peripheral region 26 increases the width of the p-type gate portion. This results in a decreased current gain of the NPN transistor which is part of the parasitic thyristor 52. From the above result, the parasitic thyristor 52 is hard to activate. Therefore, even if the output pad 11 has a negative potential to generate a surge, misoperation of the control circuit region 27 can be prevented.
FIG. 11 is an equivalent circuit diagram of the semiconductor device mentioned in Document 2.
The semiconductor device includes an input/output pad 11a electrically connected to an inductive load, and a control circuit 19. At a connecting point N21 positioned between the input/output pad 11a and the control circuit 19, a negative surge absorbing unit 13 and a positive surge absorbing unit 14 are electrically connected to each other.
Although detailed description of the negative and positive surge absorbing units 13 and 14 is omitted, they have the function of absorbing negative and positive surges, respectively, as in the case of the technique of Document 1 shown in FIG. 8.
The semiconductor device is also provided with a driver element 12. In this device, the driver element 12 is placed a sufficient distance A away from the negative surge protection diode 15.
FIG. 12 is a view exemplarily showing the plan structure of the semiconductor device which attains the equivalent circuit diagram in FIG. 11. This figure illustrates the negative surge absorbing unit 13.
Referring to FIG. 12, the semiconductor device has regions defined by the p-type isolation layer 24. Specifically, it is formed with a protection diode region 25 and a control circuit region 27 similar to those of the semiconductor device in FIG. 10.
That is to say, in this device, a negative surge protection diode 15 is formed which includes the p-type isolation layer 24, an n-type buried layer 28, and a heavily n-doped layer 29, and the heavily n-doped layer 29 is electrically connected to the connecting point N21 on an interconnect electrically connecting the input/output pad 11a to the control circuit 19.
Further, the driver element 12 surrounded with the p-type isolation region 24 is arranged a sufficient distance A away from the protection diode region 25.
In the device thus configured, if the driver element 12 has a negative potential to generate a surge, a parasitic NPN transistor may be activated which uses the n-type buried layer 28, the heavily n-doped layer 29, and the like as a collector, the p-type isolation region 24 and the like as a base, and an n-type epitaxial layer of the driver element 12 as an emitter. However, since the negative surge protection diode 15 and the driver element 12 are arranged sufficiently away from each other, the p-type isolation region corresponding to the base has a high resistance. This prevents activation of the parasitic NPN transistor. Owing to this, misoperation of the control circuit region 27 is avoided.